\doxysection{DFSDM\+\_\+\+Channel\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_d_f_s_d_m___channel___type_def}{}\label{struct_d_f_s_d_m___channel___type_def}\index{DFSDM\_Channel\_TypeDef@{DFSDM\_Channel\_TypeDef}}


DFSDM channel configuration registers.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_f_s_d_m___channel___type_def_ad59d0c9e6a23c073d5074c1080437509}{CHCFGR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_f_s_d_m___channel___type_def_a06ccb02a66ad9b39d5df801ffccdc0bb}{CHCFGR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_f_s_d_m___channel___type_def_a418e04c7b9a06d216ec9af9d040f34bb}{CHAWSCDR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_f_s_d_m___channel___type_def_a662b02dfee03cfde7809fd168626f87f}{CHWDATAR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_f_s_d_m___channel___type_def_a82d9028493b845db2391dfbec944bf2e}{CHDATINR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
DFSDM channel configuration registers. 

\label{doc-variable-members}
\Hypertarget{struct_d_f_s_d_m___channel___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_d_f_s_d_m___channel___type_def_a418e04c7b9a06d216ec9af9d040f34bb}\index{DFSDM\_Channel\_TypeDef@{DFSDM\_Channel\_TypeDef}!CHAWSCDR@{CHAWSCDR}}
\index{CHAWSCDR@{CHAWSCDR}!DFSDM\_Channel\_TypeDef@{DFSDM\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CHAWSCDR}{CHAWSCDR}}
{\footnotesize\ttfamily \label{struct_d_f_s_d_m___channel___type_def_a418e04c7b9a06d216ec9af9d040f34bb} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DFSDM\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CHAWSCDR}

DFSDM channel analog watchdog and short circuit detector register, Address offset\+: 0x08 \Hypertarget{struct_d_f_s_d_m___channel___type_def_ad59d0c9e6a23c073d5074c1080437509}\index{DFSDM\_Channel\_TypeDef@{DFSDM\_Channel\_TypeDef}!CHCFGR1@{CHCFGR1}}
\index{CHCFGR1@{CHCFGR1}!DFSDM\_Channel\_TypeDef@{DFSDM\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CHCFGR1}{CHCFGR1}}
{\footnotesize\ttfamily \label{struct_d_f_s_d_m___channel___type_def_ad59d0c9e6a23c073d5074c1080437509} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DFSDM\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CHCFGR1}

DFSDM channel configuration register1, Address offset\+: 0x00 \Hypertarget{struct_d_f_s_d_m___channel___type_def_a06ccb02a66ad9b39d5df801ffccdc0bb}\index{DFSDM\_Channel\_TypeDef@{DFSDM\_Channel\_TypeDef}!CHCFGR2@{CHCFGR2}}
\index{CHCFGR2@{CHCFGR2}!DFSDM\_Channel\_TypeDef@{DFSDM\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CHCFGR2}{CHCFGR2}}
{\footnotesize\ttfamily \label{struct_d_f_s_d_m___channel___type_def_a06ccb02a66ad9b39d5df801ffccdc0bb} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DFSDM\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CHCFGR2}

DFSDM channel configuration register2, Address offset\+: 0x04 \Hypertarget{struct_d_f_s_d_m___channel___type_def_a82d9028493b845db2391dfbec944bf2e}\index{DFSDM\_Channel\_TypeDef@{DFSDM\_Channel\_TypeDef}!CHDATINR@{CHDATINR}}
\index{CHDATINR@{CHDATINR}!DFSDM\_Channel\_TypeDef@{DFSDM\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CHDATINR}{CHDATINR}}
{\footnotesize\ttfamily \label{struct_d_f_s_d_m___channel___type_def_a82d9028493b845db2391dfbec944bf2e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DFSDM\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CHDATINR}

DFSDM channel data input register, Address offset\+: 0x10 \Hypertarget{struct_d_f_s_d_m___channel___type_def_a662b02dfee03cfde7809fd168626f87f}\index{DFSDM\_Channel\_TypeDef@{DFSDM\_Channel\_TypeDef}!CHWDATAR@{CHWDATAR}}
\index{CHWDATAR@{CHWDATAR}!DFSDM\_Channel\_TypeDef@{DFSDM\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CHWDATAR}{CHWDATAR}}
{\footnotesize\ttfamily \label{struct_d_f_s_d_m___channel___type_def_a662b02dfee03cfde7809fd168626f87f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DFSDM\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CHWDATAR}

DFSDM channel watchdog filter data register, Address offset\+: 0x0C 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
